1. Field of the Invention
The present invention relates to a method of identifying an inaccurate model of a hardware circuit and in particular but not exclusively, to an inaccurate hardware description language (HDL) model which involves analog and digital signal types.
2. Discussion of the Related Art
In the past during mixed signal IC device or “chip” development, testing departments have had to wait until a device has been reduced to silicon before functional tests can be performed. In view of the increase in the general requirements for mixed signal (using digital and analog signals) chips and their shrinking product shelf life, the need to reduce development time has risen accordingly. By testing IC device designs prior to reduction to silicon overall development times can be reduced considerably. This means that a device can be brought to market more quickly.
A number of test simulators are known which allow test departments to test how a device will function as soon as a preliminary design is completed. This can be prior to the reduction to silicon of the device.
One type of test simulator is an analog simulator which may be used for non-linear DC, non-linear transient and linear AC analysis. SPICE is an example of an industry standard general-purpose analog circuit simulator. A development of the SPICE simulator is the ELDO simulator which provides the functionality, performance and accuracy of SPICE-level simulation along with improved algorithms which allow more complex circuits to be simulated and also provides a mixed signal simulation capability.
Analog simulators, as the name suggests, allow simulation of a hardware cell being tested at the analog signal level. The simulator provides performance results through the whole range of analog input signals and allows for voltage sweeps. In other words, the cell is tested over a wide range of voltage values, the voltage values being for example applied as inputs. As a result analog simulators provide very accurate descriptions of the designed device operation. However simulation times can be prohibitively protracted especially when a design comprises many thousands or hundreds of thousands of cells to be simulated.
As a solution to the task of describing circuits of such large scale, digital simulators have been developed. Numerous digital simulators have been developed to model the behaviour of circuitry described using a hardware description language (HDL). HDL is a programming language which has been designed and optimised for simulating and thereby describing behaviour of digital circuitry. HDL allows electrical aspects of circuit behaviour to be precisely described. However since only digital signals (which have one of two states) are simulated simulation time scales are much reduced. Additionally, only changes of logic level trigger an evaluation of the effect. A specific example of HDL is the very high speed integrated circuit HDL known as VHDL.
HDL models typically provide a behavioural description of the circuitry of the designed device which can be synthesised into a net list which includes circuit diagrams of the device saved in textual form. In other words, the circuitry of the device is broken down into cells or small circuit portions, each of which has a known behaviour. These cells or small circuit portions are listed in the net list. Operation of the device is simulated by stimulating the net list by the application of a test bench. Test benches are HDL descriptions of circuit stimulus. The outputs of the cell in response to stimulus are compared with expected outputs to verify the behaviour of a circuit over time. The verification results may be analysed to establish how the circuit has functioned.
In order to decrease the simulation times it is therefore advantageous to use a digital simulator of a hardware cell or circuit. However in order to check that the digital model used is operating correctly and therefore accurately a comparison is initially made between the results from the digital model of a test circuit with the results obtained by simulating the same test circuit with an analog model. If both models of the same hardware cell produce identical results when the cell's operation is simulated, it is an indication that the models are themselves accurate.
One problem with such a comparison of results is that whilst any digital model of a hardware cell will simulate in digital format what the cell is designed to do (or what a designer wants the cell to do) an analog model will actually model what the cell does ie how it operates under different input and output conditions. In some instances the two effects are not equal. This is because the ideal state modelled by a digital model is seldom attained in practice, as modelled via the analog simulator. In fact an analog model may well provide results which vary slightly from the ideal digital model. In such a situation when a strict comparison of results of the digital and analog models is made any results which are even slightly different will indicate that at least one of the models is inaccurate and the test will fail. As a result models which are actually accurately and correctly functioning will indicate an error when a strict comparison is made between them.
Another problem is that prior systems which have allowed the results from an analog model of a hardware cell to be compared with those of a digital cell have not allowed the tool to verify mixed signal type applications. These are occasions, such as the modelling of an analog to digital converter (ADC) or digital to analog converter (DAC), in which real data types and abstract data types are required. Real data types are for example floating point data types. Also rational numbers can represent real data types. Essentially real data types are able to approximate real numbers both rational and irrational. The real data type is thus a number which can contain a fractional part. Abstract data types are described in more detail hereinafter.
VHDL supports many abstract data types which are used to describe different signal strengths or commonly used simulation conditions such as unknowns and high-impedance conditions. These non-standard data types have been adopted by the IEEE as standard 1164. Such data types are not applicable to analog simulators which require true analog signals rather than abstract data types.
It is an aim of embodiments of the present invention to at least partly mitigate the above problems.